Interrupt system for transmitting interrupt request signal and interrupt vector based upon output of synchronized counters representing selected priority value
US4994960A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 1989 |
| Grant date | Feb 19, 1991 |
| Priority date | — |
| Expiry date | Jul 10, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/225
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data transfer system including a byte bus which provides an eight-bit data transfer between a processor and a plurality of port circuit boards. The system provides dual address and interrupt functionalies in the processor-initiator data transfers which may be initiated in either direction. The processor data transfers use a two-level address management scheme, which once initialized provides rapid access to a select number of address locations from a large number of available addresses allocated to a variety of port circuit boards and addressable functions thereon. Furthermore, the select addresses are assignable according to an interrupt priority value which allows for the rapid identification of the address requesting an interrupt service, and also for the subsequent provision of an interrupt service vector to the processor to provide the appropriate processing of the requested interrupt. The resulting apparatus and method provides substantial compaction of the communication data distribution system and software driving utilities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.