Write back buffer with error correcting capabilities
US4995041A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1989 |
| Grant date | Feb 19, 1991 |
| Priority date | — |
| Expiry date | Feb 3, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In the operation of high-speed computers, it is frequently advantageous to employ a high speed cache memory within each CPU of a multiple CPU computer system. A standard, slower memory configuration remains in use for the large, common main memory, but those portions of main memory which are expected to be used heavily are copied into the cache memory. Thus, on many memory references, the faster cache memory is exploited, while only infrequent references to the slower main memory are necessary. This configuration generally speeds the overall operation of the computer system; however, memory integrity problems arise by maintaining two separate copies of selected portions of main memory. Accordingly, the memory access unit of the CPU uses error correction code (ECC) hardware to ensure the integrity of the data delivered between the cache and main memory. The prevent the ECC hardware from slowing the overall operation of the CPU, the error correction is performed underneath a write back operation. Data contained in the cache, which will be displaced by data received from main memory 10, is transferred to a write back buffer (WBB) during that period of time between the request for data…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.