Fast decision feedback decoder for digital data
US4995106A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 24, 1989 |
| Grant date | Feb 19, 1991 |
| Priority date | — |
| Expiry date | Aug 24, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/063
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The decision feedback decoder of the invention receives sequentially digital values corresponding to a data stream transmitted by a signal transmission channel. The decoder has two parallel signal paths. The first path has a first logic circuit which receives every other digital value corresponding to every other data bit of the transmitted data stream, and it provides and outputs subsequent decisions determining the values of these corresponding bits. The second path has a second logic circuit which receives sequentially all the digital values corresponding to all the data bits of the stream. During the time of providing each decision by the first logic circuit, the second logic circuit provides two subsequent decisions determining the respective values of two subsequent bits, but it outputs only every other decision, which alternates with the decisions provided by the first logic circuit. A predetermined number of previous decisions is stored and fed back to both logic circuits for use in the decision making process. The resulting rate the decisions output by the decoder of the invention is approximately doubled over the rate of known decision feedback decoders.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.