Auto-zeroing circuit for offset cancellation
US4996529A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 10, 1989 |
| Grant date | Feb 26, 1991 |
| Priority date | — |
| Expiry date | Apr 10, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/304
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved auto-zeroing feedback control circuit (FIG. 1) is disclosed to compensate for DC offset voltages in signal coding applications. The feedback control circuit for a signal limiter (120) includes a digital integrator (130) which oversamples the limited output (125). When the accumulated sample count overflows, an analog integrator (140) is enabled, and a small quantity of charge is delivered to the integrating capacitor. The analog integrator output signal (145) is then attenuated (150) and used to adjust the bias for the limiter (120). This improved auto-zeroing technique eliminates the requirement of a large external auto-zero capacitor, and permits the signal coder to be fully integrated on-chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.