Selection of divisor multipliers in a floating point divide circuit
US4996660A · kind A · utility
11Cited by
3References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1989 |
| Grant date | Feb 26, 1991 |
| Priority date | — |
| Expiry date | Apr 17, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5352
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple selector logic circuit for selecting divisor multiples in 2-bit, non-restoring divide sequences, which provides a proper and accurate quotient result and remainder, and which produces rounding and indication of exact or inexact result in conformance with ANSI/IEEE Standard 754-1985; the multiple selector logic circuit incorporates semiconductor circuits including a multiplier table having a particular matrix of multipliers which meet the standard.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.