Integrated circuit testing method and apparatus and integrated circuit devices for use therewith
US4996691A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 1988 |
| Grant date | Feb 26, 1991 |
| Priority date | — |
| Expiry date | Sep 21, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318566
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In a so-called "scan-design" arrangement for testing integrated circuits, whether at the device level or at system level, problems associated with the storage and handling of vast amounts of data from increasingly complex devices are addressed by testing a pair of identical integrated circuits simultaneously and using the binary vector generated by scanning one of these integrated circuits as the reference against which to compare the binary vector produced by scanning the other integrated circuit. A plurality of "scan-designed" integrated circuits may be connected in series, possibly in a ring, and each compared with its predecessor. Zero-display coupling across each device may be employed to allow each successive integrated circuit to be compared with the same reference circuit in the chain or ring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.