Central processing unit with improved stack register operation
US5001629A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 1987 |
| Grant date | Mar 19, 1991 |
| Priority date | — |
| Expiry date | Sep 25, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a central processing unit, one write address is made to correspond to a pair of registers, and when an instruction output from an instruction decoder is a data transfer instruction to either one of the above-mentioned pair of registers, the data held in one of the above-mentioned pair of registers is kept to be held in either register of the above-mentioned pair of registers and the data from the internal data bus is transferred to the remaining register of the pair of registers, and in response to a read instruction, data is transferred from each register to the internal data bus without changing the contents of the other register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.