Data processor with combined adaptive LMS and general multiplication functions
US5001661A · kind A · utility
20Cited by
6References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 23, 1990 |
| Grant date | Mar 19, 1991 |
| Priority date | — |
| Expiry date | Jan 23, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H21/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data processing system uses the same structure and hardware to implement either a general purpose multiplier or arithmetic operations associated with the least-mean-squares (LMS) algorithm. Multiplier and adder circuits are time-shared to perform the myriad functions. In one form, further modified Booth's algorithm is utilized so that an output product of two binary input numbers may be quickly formed by executing a series of multiplications and accumulations. The operation is pipelined for continuous processing activity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.