Addressing technique for providing read, modify and write operations in a single data processing cycle with serpentine configured RAMs
US5001665A · kind A · utility
10Cited by
9References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1986 |
| Grant date | Mar 19, 1991 |
| Priority date | — |
| Expiry date | Jun 26, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0607
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for accomplishing a read, modify and write operation of a memory in a processor in a single cycle of the processor, where a cycle is understood as the time between successive loads of operands to the processor. A memory having two distinct portions of operands is provided wherein the single cycle operations are accomplished by virtually addressing the operands in a serpentine or snake-like configuration. A decoder is provided for efficiently controlling the concurrent reading and writing of operands and controlling the addressing of the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.