Circuit technique for biasing complementary Darlington emitter follower stages
US5003198A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 1989 |
| Grant date | Mar 26, 1991 |
| Priority date | — |
| Expiry date | Sep 28, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/615
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit technique for biasing a complementary NPN-PNP Darlington Emitter Follower Stage without additional biasing resistors or current sources. Four diode-connected transistor are connected in series to provide biasing across the Darlington. Two transistors, one NPN and one PNP, are added with their bases and emitters connected in parallel with the top and bottom diodes, respectively, forming two current mirrors. The collector of the NPN transistor connects to the emitter of the first Darlington NPN transistor. The collector of the PNP transistor connects to the first Darlington PNP transistor. The current mirrors provide equal current to the two first Darlington transistors. These currents are also equal to the current through the four diodes for identically sized transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.