Dual addressing transistor active matrix display screen
US5003302A · kind A · utility
7Cited by
3References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 16, 1986 |
| Grant date | Mar 26, 1991 |
| Priority date | — |
| Expiry date | Jun 16, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Active matrix display screen comprising a matrix of display points and, between these points, addressing lines (Ln) and addressing columns (Cp), each point (Pn,p) being connected by a thin-film transistor (Tn,p) to a line (Ln) and a column (Cp). The screen is characterized by the fact that each point is further connected by a second transistor (Tn+1,p+1) to the next line (Ln+1) and to the next colunn (Cp+1). The effects of column breaks are thus eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.