Integrated circuit with high-impedance well tie
US5003362A · kind A · utility
4Cited by
2References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1989 |
| Grant date | Mar 26, 1991 |
| Priority date | — |
| Expiry date | Jul 28, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/026
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An integrated circuit which includes a series resistor in the well tie. This resistor permits the wall to be used for clamping, without large current consumption due to the parastic bipolar device in the well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.