Faulted current indicators and inrush restraints therefor
US5003426A · kind A · utility
10Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1989 |
| Grant date | Mar 26, 1991 |
| Priority date | — |
| Expiry date | Jun 30, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H1/043
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A faulted circuit indicator includes an inrush restraint circuit that suppresses a trip signal when an inrush current rises from below a minimum value to a trip value within a predetermined time and then drops again to another value such as the trip value. According to various aspects the restraint ends after a fixed time or after a variable time. According to another aspect a second trip circuit overrides the inrush restraint circuit when the current rises a given amount beyond the first trip value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.