Latching input buffer for an ATD memory
US5003513A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 1990 |
| Grant date | Mar 26, 1991 |
| Priority date | — |
| Expiry date | Apr 23, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An ATD memory has an input buffer which latches addresses while maintaining good D.C. margin, hysteresis, and transition detection. The input buffer includes two input circuits for receiving the address. A transmission-gate type latch is used to latch the outputs of the two input circuits. An internal buffer circuit receives the output of the latch and provides internal address signals useful to a decoder in selecting a memory cell. The internal buffer circuit also provides slow and fast signals useful in performing transition detection. The latch either provides outputs responsive to the address signal or an output representative of the address signal at the time a latch enable signal is received.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.