Error correction coding and decoding circuit for digitally coded information
US5003540A · kind A · utility
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5References
3Claims
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Key dates
| Filing date | Aug 31, 1988 |
| Grant date | Mar 26, 1991 |
| Priority date | — |
| Expiry date | Aug 31, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/43
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An error correction coding and decoding circuit for digitally coded information in which a majority difference set cyclic code is used to apply error correction coding and decoding to a data signal having data bits suitably assigned to information bits and parity bits, characterized in that a clock signal (CLKC) for the internal operation of the circuit, a data load clock signal for loading data onto the circuit, and a data read clock signal for reading data from the circuit are delivered from an external circuit provided separately from the error correction coding and decoding circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.