Method for manufacturing a semiconductor device having a phospho silicate glass layer as an interlayer insulating layer
US5004704A · kind A · utility
37Cited by
5References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1989 |
| Grant date | Apr 2, 1991 |
| Priority date | — |
| Expiry date | Oct 30, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/133
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A Phospho Silicate Glass layer is used for an insulation layer between a lower wiring layer including a refractory metal silicide and an upper wiring layer in a semiconductor device of a multilevel interconnection structure. A reflow treatment is performed on the Phospho Silicate Glass layer using steam. A part of the lower wiring layer is oxidized during the reflow treatment, and the resistivity of the lower wiring layer is simultaneously lowered during the reflow treatment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.