Hybrid phase-locked loop

US5005016A · kind A · utility

Assignee

• U.S. Philips Corporation · US

Inventors

• Konrad Schmidt · Ellingen, DE
• Ralf-Martin Kramer · Nuremberg, DE

Key dates

• Filing date: Mar 27, 1990
• Grant date: Apr 2, 1991
• Expiry date: Mar 27, 2010

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03L7/093
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

The invention relates to a phase-locked loop comprising a phase detector (PD), an analog-to-digital converter (ADC), a loop filter (LF), a digital-to-analog converter (DAC) and a voltage-controlled oscillator (VCO). The phase jitter that occurs in such a hybrid phase-locked loop is reduced without enhancing the requirements as to the resolution of the digital-to-analog converter (DAC), in that a fractionizer (FR) is inserted after the loop filter (LF) that is operating at a first clock (TL), which fractionizer produces a main value (HW) and a residual value (RW), and the sum (SW) of the main value (HW) and a correction bit (KB) derived from the residual value (RW) is applied to the digital-to-analog converter (DAC) that is operating at a second clock (TA).