BIMOS logic gates
US5006730A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 21, 1990 |
| Grant date | Apr 9, 1991 |
| Priority date | — |
| Expiry date | Sep 21, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/017527
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A BIMOS logic gate (10) comprises a differential circuit having a common biasing network (14). A MOS transistor (16) in one portion of the differential circuit receives a MOS level input signal (36) and provides an ECL level output signal (34). A bipolar transistor (20) is biased by a complementary ECL level input signal 32'. The other portion of the differential circuit includes a bipolar transistor (30) that is biased by an ECL level input signal 32. The emitter coupled transistors 20 and 30, receiving complementary ECL level inputs, along with the MOS transistor 36, receiving MOS level inputs, combine to provide logic functions with ECL level outputs 34 and 34'.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.