Delay circuit for integrated circuit
US5006738A · kind A · utility
13Cited by
9References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 1990 |
| Grant date | Apr 9, 1991 |
| Priority date | — |
| Expiry date | Jun 13, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00195
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay circuit for integrated circuits includes a current mirror circuit having at least a pair of MIS transistors, a constant current source and a capacitance. The delay time is determined by the charging time of the capacitance connected to one of the MIS transistors. A stable delay time is obtained regardless of manufacturing variations and the space required for the circuit is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.