Track and hold phase locked loop circuit
US5006819A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 1990 |
| Grant date | Apr 9, 1991 |
| Priority date | — |
| Expiry date | May 21, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop circuit including ramp generating circuitry for generating a dual slope ramp signal having alternating positive and negative slopes that are controlled by the level of the control signal, and sampling circuitry responsive to sample command pulses for providing a sample output representative of the level of the dual ramp signal at the time of sampling. The sample output is provided to a loop which provides the control signal for the ramp generating circuit. Also disclosed is a phase locked loop having ramp generating circuitry for generating a ramp signal, and track and hold circuitry having a plurality of track/hold capacitors that are controlled to track the ramp voltage or hold the ramp signal voltage in response to a sample command signal, such that only a capacitor that is tracking is switched to hold the ramp voltage in response to the sample command signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.