Device for reducing the redundancy in blocks of digital video data in DCT encoding
US5006930A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 1990 |
| Grant date | Apr 9, 1991 |
| Priority date | — |
| Expiry date | Mar 6, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/146
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A converter processes a digital video signal according to a known redundancy reducing algorithm executed on successive block for each frame or field and generates a transformed signal which is applied to a quantizer adapted to generate a quantized signal at preset transition levels on opposed sides of the zero, including the zero ( . . . ,-3,-2,-1, 0, 1, 2, 3, . . . ). The quantized signal is processed by a processor, adapted to determine the block length and the consecutive zero sequences along a preset scanning order, and to output a symbolic signal constituted by symbols indicating the quantization levels of the non-null data, the zero sequences and a symbol indicating the block end. The symbolic signal is applied to a variable length VLC encoder, adapted to encode data according to a preset designation law for generating a signal which is applied to a transmission buffer. The quantized signal generated by the quantizer further includes two ambiguous levels (x1 and x-1) at input values falling within respective preset intermediate ranges respectively between the zero level and the first positive level and between the zero level and the first negative level; the processor transfo…
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