Pipelined digital CPU with deadlock resolution
US5006980A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 1988 |
| Grant date | Apr 9, 1991 |
| Priority date | — |
| Expiry date | Jul 20, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipelined CPU employs separate microinstruction pipelines for the execution unit and memory management unit. Deadlocks can occur in a pipelined CPU when there is data dependency in two consecutive instructions. The later instruction may stall the pipeline if operands fetched by an earlier instruction are needed, but the earlier instruction is not producing the memory request for the operands because the pipeline is stalled; this results in a deadlock. Using separate micro-pipelines, the earlier instruction is advanced independently of the rest of the pipeline, in the case of a deadlock, so that the operands for the later instruction are provided and the deadlock is broken.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.