Method of increasing the bandwidth of a packet bus by reordering reply packets
US5006982A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Oct 21, 1988 |
| Grant date | Apr 9, 1991 |
| Priority date | — |
| Expiry date | Oct 21, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor bus in which information is transferred between agents attached to the bus by issuing request packets that request data from an agent on the bus and reply packets that return data requested by a request packet. A control method mixes request-and-reply packets on the bus by determining the use of a next-bus cycle using arbitration, reply deferral, and specification lines and the state of a grant queue and a pipe queue in accordance with a specified protocol. A request is forced to take the next available bus cycle upon the condition that there is an agent identified in the great queue and the pipeline queue is not full. A reply packet is forced to take the next available bus cycle upon the condition that the pipeline queue is full. A reply packet is forced to take the next available bus cycle upon the condition that the grant queue is empty and the pipeline queue is not empty. Giving requests precedence over replies to allows the pipeline to be kept as full as possible. A replying agent assigned to the highest priority slot 1 in the pipeline queue is allowed to defer its own slot in the pipeline queue until a later time to thereby permit a transaction in Slot 2 of t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.