Power and signal line bussing method for memory devices
US5007025A · kind A · utility
20Cited by
4References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1989 |
| Grant date | Apr 9, 1991 |
| Priority date | — |
| Expiry date | Mar 31, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell device having circuitry located between memory cell arrays comprises power and ground lines to the circuitry formed directly above the memory cell arrays. The power and ground lines are parallel and positioned in an adjacent alternating pattern such that a power line is positioned adjacent a ground line, which is positioned adjacent another power line and so on. Signal lines carrying signals to and from the circuitry are also formed directly above memory cell arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.