Apparatus for low skew system clock distribution and generation of 2X frequency clocks
US5008636A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 1988 |
| Grant date | Apr 16, 1991 |
| Priority date | — |
| Expiry date | Oct 28, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/16
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generation circuit on each circuit board of a computer system and which removes board-to-board system skew in clock signal distribution. A phase-locked loop is employed to maintain synchronization between the system reference clock signal distributed to each board and the outputs of the distribution gate array in the generation circuit on each board. A 2X frequency clock is provided by combining the clock signal with a delayed version of itself. A second order loop is employed to monitor the duty cycle of the 2X frequency clock and to adjust the duty cycle of the regular frequency clock to provide cycle-to-cycle symmetry for the 2X frequency clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.