Apparatus adding values represented as residues in modulo arithmetic
US5008849A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 1989 |
| Grant date | Apr 16, 1991 |
| Priority date | — |
| Expiry date | May 1, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/722
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an arithmetic apparatus operands are represented as powers of a generator so that multiplications can be performed as simple additions. However this makes actual addition difficult. Additions are therefore performed by means of a subtractor circuit (1), a Zech table (2) and an adder circuit (3). In order to perform these additions when each power is in plural residue form (x.sub.1, x.sub.2 and y.sub.1, y.sub.2) and give the result power also in plural residue form (i.sub.1, i.sub.2), the subtractor circuit comprises subtractor subcircuits (1A, 1B), the adder circuit comprises adder subcircuits (3A, 3B) and the Zech table is arranged to produced its output also in plural residue form (j.sub.i, j.sub.2). In order to obtain the correct result even when the power representation y.sub.1, y.sub.2 represents an operand value of zero the apparatus also includes a detector (58) for this condition, this controlling a multiplexer (61) which then conducts the other operand (x.sub.1, y.sub.1) to the output (14A', 14B'). The Zech table may be modified so that the apparatus performs subtractions rather than additions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.