Encryption apparatus
US5008938A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 1990 |
| Grant date | Apr 16, 1991 |
| Priority date | — |
| Expiry date | Mar 9, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/12
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An encryption circuit that operates with substantially zero delay. Using programmable keys and polynomials, the encryption algorithm can be constantly changed to thwart any unintended receiving parties from decoding the data. A key (101) and a polynomial (102) are loaded into registers. The key is then loaded into a shift register and shifted through XOR gates (106) at a programmable rate. The other input of the XOR gates come from the result of ANDing (103) a disable signal, the polynomial register (102), and the last stage of the shift register (104). Eight bits of the shift register outputs are XOR'ed with the input data to be encrypted. The output of these XOR gates (105) is the encrypted data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.