Dynamic semiconductor memory device formed by 2-transistor cells
US5010519A · kind A · utility
22Cited by
1References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 1988 |
| Grant date | Apr 23, 1991 |
| Priority date | — |
| Expiry date | Nov 4, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An FIFO memory comprises two-transistor type memory cells. Each of the memory cells comprises a first transistor, a second transistor and storage capacitance. The storage capacitance is connected to a first bit line through the first transistor and connected to a second bit line through the second transistor. The first transistor has its gate connected to a first word line, and the second transistor has its gate connected to a second word line. Data is written or read out through the first transistor, and data is read out or written through the second transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.