High speed ECL to CMOS translator having reduced power consumption
US5012136A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 1989 |
| Grant date | Apr 30, 1991 |
| Priority date | — |
| Expiry date | Dec 4, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00376
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed voltage translator provides a CMOS output signal in response to an ECL input signal which is applied to an input stage coupled between first and second power supply conductors wherein the potential developed at the output of the input stage is independent of variations in the power supply voltage. The translating stage is coupled between said first and second power supply conductors and is responsive to the potential developed at the output of the input stage for conducting a predetermined current therethrough. A feedback signal proportional to the magnitude of the predetermined current flowing through the translating stage is generated to control the potential developed at the output of the input stage so as to maintain the predetermined current at a low value to reduce the power consumption of the voltage translator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.