System for testing internal nodes
US5012180A · kind A · utility
40Cited by
13References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 17, 1988 |
| Grant date | Apr 30, 1991 |
| Priority date | — |
| Expiry date | May 17, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The testing circuit for testing internal nodes of a device includes storage for storing the test addresses of selected internal nodes in the device. A decoder responds to a test command from a microprocessor for selecting the test addresses from the storage and supplies the test addresses to an address bus in place of other addresses supplied to the address bus. A test decoder responds only to the test addresses on the address bus for enabling the transfer of data between the selected internal nodes in the data bus for testing the selected internal nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.