Complementary output circuit for logic circuit
US5013937A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 15, 1989 |
| Grant date | May 7, 1991 |
| Priority date | — |
| Expiry date | May 15, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01707
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output circuit for a high speed and low power logic circuit is disclosed. The logic circuit performs a logic operation on a plurality of input data signals supplied thereto and produces true and complementary intermediate output signals, the logic high level of the intermediate output signal being lower than a first power voltage and the logic low level thereof being substantially equal to a second power voltage. The output circuit includes a P-channel MOS transistor having a gate supplied with the complementary intermediate output signal, a source connected to a power voltage supplied with the first power voltage and a drain connected to an output terminal, and an N-channel MOS transistor having a gate connected to the power terminal, a source supplied with the true intermediate output signal and a drain connected to the output terminal, and thus produces at the output terminal an output signal having a logic amplitude between the first and second power voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.