Clock supply circuit having adjustment capacitance
US5013942A · kind A · utility
29Cited by
6References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 17, 1989 |
| Grant date | May 7, 1991 |
| Priority date | — |
| Expiry date | Aug 17, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a clock supply circuit operating in a first phase and a second phase. Each buffer provided in each channel operating in the second phase has the same drive ability, and the number of flip-flops which are dependent on each buffer is the same. When the number of the flip-flops is not the same, capacitance means is provided in each channel in order to make conditions uniform for operation in the second phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.