Frame synchronizer for detecting misframes with different shift patterns
US5014272A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 11, 1989 |
| Grant date | May 7, 1991 |
| Priority date | — |
| Expiry date | Aug 11, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0608
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A frame synchronizer is adapted to receive an incoming high-speed TDM (time division multiplex) signal of a framed structure containing, at frame intervals, a sequence of identical synchronization bit patterns and a sequence of byte-length data signals. A demultiplexer decomposes the high speed TDM signal into the synchronization bit patterns and the byte-length data signals and supplies them as low-speed frames to output ports. A plurality of bit pattern detectors are provided for respectively detecting different bit patterns which are successively obtained from the decomposed synchronization bit patterns when timing of the demultiplexer is successively delayed or advanced with respect to the incoming TDM signal. Each of the different bit patterns is an n-bit shifted version of the decomposed synchronization bit patterns, where n is an integer representing the amount of the delay or advance. In accordance with the detected different bit patterns, the timing of the demultiplexer is controlled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.