High speed charge-coupled sampler and rate reduction circuit
US5015876A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 1989 |
| Grant date | May 14, 1991 |
| Priority date | — |
| Expiry date | Jun 30, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high speed charge-coupled sampler and rate reduction circuit is disclosed. The present invention allows measurement of high frequency input signals while reducing actual data rates for a series of accurately interleaved sampler data streams. The charge-coupled sampler includes a source means for providing a steady supply of charge and a sampling gate means adjacent to the source means for dividing the charge stream into discrete charge packets separated uniformly in time. An input gate means, adjacent to the sampling gate means, modulates the discrete charge packets, such that size of each charge packet is directly proportional to the instantaneous voltage applied to the input gate means. A plurality of sequential charge output means in turn surround and are adjacent to the input signal gate means. Each sequential charge output means comprises a transfer gate and a storage gate for transferring and storing the charge packet modulated by the input gate means. Once a charge packet is stored by storage gate, it is available for further processing as part of that particular data stream. By interleaving the data streams from all sequential charge output means, the original input signa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.