Low distortion sample and hold circuit
US5015877A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 13, 1990 |
| Grant date | May 14, 1991 |
| Priority date | — |
| Expiry date | Apr 13, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sample and hold circuit having low distortion at a large full power bandwidth utilizes a compensation capacitor which is connected across the input and output of an output stage of the sample and hold circuit and is driven by the output current signal, i.e. slew current I.sub.S, of the input stage. A hold capacitor is also included and arranged in parallel with the compensation capacitor to be voltage driven. The hold capacitor has a capacitance much larger than that of the compensation capacitor and a voltage equal to voltage of the compensation capacitor. A switchable voltage buffer for isolating the hold capacitor from the output of the input stage and for driving the hold capacitor, independently from the slew current, to a voltage value equaling the voltage of the compensation capacitor is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.