Binary division of signed operands
US5016210A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1989 |
| Grant date | May 14, 1991 |
| Priority date | — |
| Expiry date | Nov 15, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5353
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A divider unit (15), having a divider circuit (16) and a divider controller (17), generates signed quotient and signed remainder signals in response to input signed dividend and signed divisor signals. The divider circuit (16) has an adder/subtracter unit (22), a mux (24), a zero/sign detector unit (23), and a shiftable register (28) which are controlled by the divider controller (17) and which cooperate to iteratively generate signed partial remainder and signed partial dividend signals, necessary for the computation of signed quotient and signed remainder signals, using either a restoring or non-restoring binary division algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.