Decoder for a floating gate memory
US5016216A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 17, 1988 |
| Grant date | May 14, 1991 |
| Priority date | — |
| Expiry date | Oct 17, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/781
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array of floating gate transistors is arranged so that in the transistors within the even numbered rows, the bit line on the left side of the transistor serves as the drain, and the bit line on the right side of the transistor serves as the source, and the floating gate extends over the left side of the transistor channel. Conversely, in the odd numbered rows, the bit line on the right side of each transistor serves as the drain, the bit line on the left side of each transistor serves as the source, and the floating gate extends over the left side of the transistor channel. Thus, in order for the bit line decoder to determine which bit line is to be grounded and which bit line is to be connected to a sense amplifier, the bit line decoder also receives signals indicative of the row which has been addressed. In one embodiment, the array comprises redundant rows. The decoder is constructed so that any redundant rows can be used to replace either an odd or even-numbered row in the array. The array also includes a dummy transistor column. Means are provided for coupling a transistor from the dummy transistor column to the sense amplifier which has a floating gate on the same side of …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.