Method for forming variable width isolation structures
US5017999A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1989 |
| Grant date | May 21, 1991 |
| Priority date | — |
| Expiry date | Jun 30, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/763
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An isolation structure as well as a method for using and fabricating an isolation structure in an active layer deposited on a substrate the method of fabrication including the steps of forming a buried oxide layer in the active layer adjacent the substrate, forming an isolation trench in the active layer by etching at least up to and optionally into the substrate, forming a dielectric isolation layer on the exposed surfaces of the trench, removing the dielectric isolation layer from the bottom of the trench, and forming an isolation structure by epitaxially growing monocrystalline silicon in the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.