Read-only memory for a gate array arrangement

US5018103A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Michael Pomper · Schliersee, DE
• Martin Geiger · Morton, US

Key dates

• Filing date: Aug 25, 1989
• Grant date: May 21, 1991
• Expiry date: Aug 25, 2009

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B20/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Basic cells (GZ) that are composed of at least three p-channel transistors (TP) and of three n-channel transistors (TN) are employed for constructing a read-only memory. Only the outwardly disposed transistors (TP1, TP2) or, respectively, TN1, TN2) are employed for storing the information, whereas the inwardly disposed transistors (TN3, TP3) are not used. An information is stored in that the gate electrode (G) of one transistor (TP, TN) is connected to a word line (W), the drain electrode is connected to a bit line and the source electrode is connected to a fixed supply voltage (VDD, VSS) or is not connected thereto. The layout of the basic cell (GZ) is executed such that the gate terminals ensue in the inner region of the basic cell and the word lines (W) and bit lines (B) are conducted over the basic cell perpendicularly relative to one another. Read-only memories of arbitrary size can be realized by joining such basic cells in rows and columns.