TTL to CMOS buffer circuit
US5019729A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 1989 |
| Grant date | May 28, 1991 |
| Priority date | — |
| Expiry date | Jul 21, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01855
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer circuit includes first and second differential amplification type buffer circuits. The input nodes of the first and second differential amplification type buffer circuits are connected together and the output nodes of the first and second differential amplification type buffer circuits are also connected to each other. The first differential amplification type buffer circuit is constituted by a pair of driving P-channel MOS transistors and N-channel MOS transistors acting as loads of the P-channel MOS transistors and connected to constitute a current mirror circuit. The second differential amplification type buffer circuit is constituted by P-channel MOS transistors acting as loads and connected to constitute a current mirror circuit and a pair of driving N-channel MOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.