Nonvolatile SNOS memory cell with induced capacitor
US5020030A · kind A · utility
Inventor
Key dates
| Filing date | Oct 31, 1988 |
| Grant date | May 28, 1991 |
| Priority date | — |
| Expiry date | Oct 31, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/69
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A silicon substrate with a drain area formed therein is used for the base of the device. A first polysilicon gate is disposed above the substrate with a layer of gate oxide therebetween. Adjacent to the first gate and contiguous to the same plane is a second polysilicon gate. The second gate and the substrate are separated by a layer of tunnel oxide and silicon nitride. The silicon nitride being used to store a charge. The state of the device is determined by the presence of a capacitance in the substrate generated by the charge on the silicon nitride. This device may function as a nonvolatile memory or a dynamic random access memory with the capability of capturing its DRAM state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.