High speed inverting hysteresis TTL buffer circuit
US5021687A · kind A · utility
3Cited by
5References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 1, 1990 |
| Grant date | Jun 4, 1991 |
| Priority date | — |
| Expiry date | Feb 1, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00353
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A TTL inverter buffer circuit is provided with a switched current that produces hysteresis in the threshold values. The current is switched on by a control circuit when the input logic is low and off when the logic is high. The control circuit receives its sense from the logic state so that when the input logic is low a high threshold is created and when the input logic is high a low threshold is created. The difference is the circuit hysteresis voltage which is dependent upon the switched current and a resistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.