Integrator circuit
US5021692A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 4, 1989 |
| Grant date | Jun 4, 1991 |
| Priority date | — |
| Expiry date | Dec 4, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bilinear integrator circuit includes a first input (1) and a second input (5) with the first input connected to the input of a first current memory cell formed by two transistors (T1, T2), a capacitor (C1), and a switch (S1). The first current memory cell is arranged to store a current applied to its input during a first portion .phi. of each sampling period and to reproduce that current at its output during a second portion .phi. of the succeeding sampling period. The second input is connected via a further switch (S2) to the input of a second current memory cell formed by three transistors (T3, T4 and T5), capacitor (C2) and a switch (S3). During a second portion .phi. of each sampling period the current applied to the second input and the current produced at the output of the first current memory cell are applied to the input of the second current memory cell. The second current memory cell has two outputs (from the drain electrodes of transistors T4, T5). The first output (from T4) is fed back to the input of the first current memory cell while the second output (at T5) is coupled to the integrator output (8).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.