Biasing networks for matrix amplifiers

US5021743A · kind A · utility

Assignee

• Raytheon Company · US

Inventors

• Shiou L. L. Chu · Bedford, US
• Yusuke Tajima · Tokyo, JP
• Manfred Schindler · Borgo San Lazzaro, DE

Key dates

• Filing date: Nov 30, 1989
• Grant date: Jun 4, 1991
• Expiry date: Nov 30, 2009

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03F3/607
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A radio frequency matrix amplifier includes an input propagation network for successively connecting input electrodes of a first plurality of transistors. Output electrodes are successively coupled by an intermediate propagation network. The amplifier also includes a second plurality of transistors, having input electrodes successively coupled by the intermediate propagation network and output electrodes successively coupled by an output propagation network. A bias circuit for the amplifier includes an inductor connected between a last one of the second plurality of transistors and the intermediate propagation network and a plurality of capacitors disposed to connect reference electrodes of the second plurality of transistors to a reference potential. With this arrangement stages are connected in series for D.C. potentials and in cascade for r.f. potentials. In a preferred embodiment, capacitors are disposed between the input electrodes of each of the second plurality of transistors and the output electrodes of each of the first plurality of transistors to D.C. isolate the stages, and a voltage divider is disposed between the drain bias terminal and a reference potential for balanc…