Semiconductor device and process fabrication thereof
US5021845A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 29, 1990 |
| Grant date | Jun 4, 1991 |
| Priority date | — |
| Expiry date | Jun 29, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/292
Abstract
An insulated-gate field-effect transistor device characterized by the channel region consisting of the intermediate heavily doped portion (50; 72) and two lightly doped portions (46, 48; 74,76) provided on both sides of the heavily doped portion. Such a field-effect transistor device is advantageous in that it provides a surface potential locally increased to act as an energy barrier to minority carriers. This permits control over the threshold voltage of a MOS transistor or over the punch-through current of a punch-through transistor without having recourse to the use of a high carrier density throughout the channel region. The carrier density of the channel region being rather reduced, not only reduction in leakage current but improvement in withstand voltage characteristics can be achieved in a device according to the present invention. Where the transistor device is implemented as a trench-type device, the channel region composed of the differentially doped three portions is formed along a side wall of a trench in the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.