Non-volatile semiconductor memory device with facility of storing tri-level data
US5021999A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1988 |
| Grant date | Jun 4, 1991 |
| Priority date | — |
| Expiry date | Dec 9, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5612
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory cell includes a MOS transistor of double gate construction. The MOS memory transistor includes a floating gate structure which includes electrically separated first and second segmented floating gates (4a; 4b). For the purpose of writing data, electrons are independently injected into the first and second segmented floating gates. Data are stored in the MOS memory transistor in three different non-volatile storage levels; one with electron accumulated either one of the two segmented floating gates; another with electrons injected into both of the segmented floating gates; and still another with no electrons accumulated on both of the segmented floating gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.