Method and apparatus for DRAM memory performance enhancement
US5022004A · kind A · utility
41Cited by
4References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 28, 1988 |
| Grant date | Jun 4, 1991 |
| Priority date | — |
| Expiry date | Oct 28, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is disclosed for improving the performance of a digital computer by reducing the latency of read operations and increasing available write bandwidth by utilizing a subset of the address bits which are the same from one operation to the next. A faster cycle type (e.g. page mode or static column) can thereby be employed in the Dynamic Random Access Memory (DRAM) memory by eliminating the DRAM precharge and RAS address portions of the cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.