Redundant encryption processor arrangement for use in an electronic fund transfer network
US5022076A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1988 |
| Grant date | Jun 4, 1991 |
| Priority date | — |
| Expiry date | Dec 9, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG07F7/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved fault tolerant processor arrangement is described. In accordance with this invention, redundant processors are coupled in parallel in a master/slave configuration wherein means are provided for disabling the respective outputs of the processors. The master processor includes means for generating a periodic pulse which is detected by the slave processor. As long as the periodic pulse is detected by the slave processor, the output of the master processor remains enabled and the output of the slave processor is disabled. If the periodic pulse is not detected by the slave processor, the slave processor disables the output of the master processor wherein the output of the slave processor becomes enabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.