Architecture of high speed synchronous state machine
US5023484A · kind A · utility
63Cited by
12References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 1989 |
| Grant date | Jun 11, 1991 |
| Priority date | — |
| Expiry date | Oct 31, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17716
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved architecture for and a method of operating a high speed synchronous state machine is disclosed having a programmable logic array receiving inputs from dedicated input registers and having an input/output macrocell which includes two state registers and two input registers, and two transparent latches and two feedback multiplexers. The outputs from the input registers are multiplexed through an input multiplexer and the input registers may be clocked at different input clock rates than the state clock which clocks the state registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.