ECL/TTL-CMOS translator bus interface architecture
US5023487A · kind A · utility
14Cited by
8References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1989 |
| Grant date | Jun 11, 1991 |
| Priority date | — |
| Expiry date | Sep 29, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/017581
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Described is an architecture for translating between ECL and TTL/CMOS signal levels in which the control signal applied to the translating circuitry is of the same type as the output signal of the device in which the architecture is used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.